| 摘要 |
PROBLEM TO BE SOLVED: To transfer data from a memory to a register with simple processing at a high speed. SOLUTION: This data transfer device is provided with a decoder 2 for decoding an instruction issued from an instruction cache 1, a cache memory 3 for 32-bit read and write, a long register 4 having 128-bit data achieving 32-bit read and write, a control part 5 for controlling data transfer from the cache memory 3 to the long register 4, a mask control part 6 for inhibiting writing on data stored in the long register 4 and a sequence change computing element 7 for changing the data stored in the long register 4. Even if a start address of the transfer data deviates from a 32-bit boundary position of the cache memory 3, only one instruction is required to instruct the data transfer from the cache memory 3 to the long register 4, so that the number of instructions can be reduced. Since transfer processing when the start address deviates from the 32-bit boundary position is performed by hardware, it is not required to consider in software whether the start address of the transfer data deviates from the 32-bit boundary position. COPYRIGHT: (C)2008,JPO&INPIT
|
