| 摘要 |
A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows ( 702, 704, and 706 ) and columns ( 750, 752 ). A first conductor ( 710, 850 ) is coupled to a plurality of the rows ( 702, 704, and 706 ) of memory cells. A first transistor ( 810 ) has a current path coupled between a voltage supply terminal ( 800 ) and the first conductor ( 850 ) and a control terminal coupled to receive a first control signal (PLV). A second transistor ( 820 ) has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).
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