| 摘要 |
A D/A converter with reduced power consumption is offered by reducing an amount of electric charges that is charged and discharged as D/A conversion is performed. A terminal of each of four capacitors C 1 , C 2 , C 3 and C 4 is connected to a common node. The capacitors C 1 , C 2 , C 3 and C 4 have capacitances C, C, 2C and 4C, respectively. A selection circuit SEL is provided with selection transistors ST 1 , ST 2 , ST 3 , ST 4 , ST 5 and ST 6 , and selects and outputs either a first reference electric potential V 1 or a second electric potential V 2 according to a value of each bit of the digital signals D<SUB>0</SUB>, D<SUB>1 </SUB>and D<SUB>2</SUB>. Each of transfer transistors TT 1 , TT 2 and TT 3 transfers each of outputs of the selection circuit SEL to another terminal of corresponding each of the capacitors C 2 , C 3 and C 4 , respectively, in response to a start pulse STP. Each of reset transistors RT 1 , RT 2 , RT 3 and RT 4 connects the terminal with the other terminal of corresponding each of the capacitors C 1 , C 2 , C 3 and C 4 , and applies the first reference electric potential V 1 to both the terminal and the other terminal in response to a reset pulse RST.
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