DELAY CIRCUIT, JIGGER-APLLIED CIRCUIT, AND TESTER

摘要

A delay circuit for delaying and outputting a given input signal comprises a first delay portion for delaying the input signal by the amount of a delay corresponding to a supplied delay control signal, a second delay portion for further delaying the input signal delayed by the first delay portion by the amount of the delay corresponding to the supplied delay control signal, and a delay setting portion for supplying the delay control signal to the first delay portion, delaying the delay control signal, and supplying it to the second delay portion.