| 摘要 |
<p>To level the power consumptions of semiconductor integrated circuits. An in-phase clock signal (CLK1) is supplied to a first calculation block group, while an opposite-phase clock signal (CLK2), which is obtained by inverting the in-phase clocks (CLK1), is supplied to a second calculation block group. A circuit is provided which converts data synchronized with the opposite-phase clock signal (CLK2) to data synchronized with the in-phase clock signal (CLK1). A timing at which the power consumption of a calculation block group operating in synchronism with the in-phase clock signal (CLK1) reaches its maximum value differs by a half period from a timing at which the power consumption of a calculation block group operating in synchronism with the opposite-phase clock signal (CLK2) reaches its maximum value, so that the maximum value of the power consumption of a semiconductor integrated circuit (10) can be reduced to level the power consumption.</p> |
