发明名称 DELAY FAILURE ANALYSIS METHOD AND ITS DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a technique capable of specifying a bottleneck circuit part in frequency performance quickly and uniquely in analyzing delay failure of an integrated circuit. SOLUTION: The method includes: obtaining the region code (RC) of the maximum generation frequency among the region codes belonging to a check circuit detecting errors generating when an operation clock frequency applying on an integrated circuit is increased gradually; acquiring the latch information generating errors in the RC of the maximum generation frequency with referring to the corresponding table describing the corresponding relation between RC and latch; back tracing comprehensively the circuit part connected with the latch from acquired each latch as a start point to the latches described in the corresponding table; extracting the circuit part where errors are detected in the RC of the maximum generation frequency; and applying a delay failure on each input-output pin of each logic element involved in the circuit part to perform a delay test with forming a test pattern to detect the delay failure. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008076121(A) 申请公布日期 2008.04.03
申请号 JP20060253651 申请日期 2006.09.20
申请人 FUJITSU LTD 发明人 ITO NORIYUKI
分类号 G01R31/317;G01R31/3183 主分类号 G01R31/317
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