| 摘要 |
A system comprises a memory controller which schedules read commands via a first dedicated command slot and write commands and data to dedicated second or third command slots. These slots, or logical channels, are used in conjunction with a scheduling system which queues read and write commands, making use of logic to resolve any conflicts in a manner akin to an arbitration circuit. The system is designed so that there are no idle frames when write commands are issued and is particular suitable for systems in which fully buffered DIMMs are used. |
