| 摘要 |
A semiconductor memory device (20) includes a timing signal circuit (21) to generate a refresh timing signal comprised of a series of pulses, a refresh address circuit (22) to generate a refresh address in synchronization with each pulse of the refresh timing signal, a pulse selecting circuit (31) to assert a refresh request signal in synchronization with pulses selected from the series of pulses, and a memory core (24) to receive the refresh address and the refresh request signal and to perform a refresh operation with respect to the refresh address in response to assertion of the refresh request signal, wherein arrangement is made to switch between a first operation mode in which the selected pulses are obtained by selecting one pulse out of every predetermined number of pulses from the series of pulses and a second operation mode in which the selected pulses are obtained by selecting consecutive pulses from the series of pulses.
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