| 摘要 |
A layout method of a semiconductor device is provided to minimize a process deviation by disposing dummy gates in view of a distance of spaced transistors and a length of a periphery gate. At least one gate for forming a transistor is formed on a substrate. Dummy gates(DG1 to DG2) are formed on the same layer as the gate to have the same length as the gate, and are spaced apart from each other on sides of the gate. An auxiliary dummy gate is formed on the same layer as the gate, and is spaced apart from the gate. The auxiliary dummy gate is integrally formed with the dummy gates. The auxiliary dummy gate is formed in a rectangular shape on one end of the dummy gate, and has a width larger than that of the dummy gate.
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