| 摘要 |
A circuit arrangement for generating switch-on signals for driving track-and-hold elements of an analog-to-digital converter operating with interleaved timing comprises a first input for inputting a common reference clock signal, at least one window device for generating clock signals which are interleaved with respect to one another in terms of timing and whose respective time windows in which the respective of the clock signals has a first logic level are derived from the reference clock signal, and at least one gate device for generating a switch-on signal. The gate device is connected downstream of the window device and combines logically the reference clock signal with a respective of the clock signals and with a further information item so that a time window of the switch-on signal is at least longer than the window of the reference clock signal.
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