发明名称 Analog delay circuit
摘要 An analog delay circuit to impart a group delay to an analog input signal is described. The analog delay circuit may comprise a capacitor to impart at least a portion of the group delay to the analog output signal and a buffer circuit coupled between the capacitor and an input stage to substantially remove at least a portion of a capacitive load at the input stage.
申请公布号 US7352826(B2) 申请公布日期 2008.04.01
申请号 US20030741001 申请日期 2003.12.19
申请人 INTEL CORPORATION 发明人 KRISHNASWAMI ANUSH A.
分类号 H03K9/00;H03H11/26;H03H15/00 主分类号 H03K9/00
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