Clock signal generator for Universal serial bus device, has control circuit for generating frequency control signal based on count value, where generator generates clock signal having frequency corresponding to frequency control signal

摘要

The generator (250) has a control circuit for counting cycles of a clock signal during each period between two sequentially input synchronization signals. The control circuit generates a frequency control signal based on a count value. The generator generates the clock signal having a frequency corresponding to the frequency control signal. The control circuit blocks the frequency control signal, when the count value in a predetermined range. Independent claims are also included for the following: (1) a method for generating a clock signal (2) a circuit comprising a transceiver.