| 摘要 |
PROBLEM TO BE SOLVED: To provide a drawing apparatus having a plurality of heads, wherein a circuit scale of a circuit to generate a plurality of timing signals (drawing enabling signals) for controlling the respective heads, is reduced. SOLUTION: A current address holding section 240 holds a current address representing an address of a writing destination at the time of memory writing processing, and the current address is increased one by one for every pulse generation of the drawing timing signals TG. A memory writing processing section 223 writes a value of a reference drawing enabling signal KS to the current address of a memory 250 for every pulse generation of the drawing timing signals TG. A drawing enabling signal generation section 224 acquires a reference address in the memory 250, based on parameters P(2) to P(N) representing the number of drawing bits between the second to the N-th heads HD(2) to HD(N), and the first head HD(1), and generates the second to the N-th drawing enabling signals KY(2) to (N), based on the value of the reference address. COPYRIGHT: (C)2008,JPO&INPIT
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