| 摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM memory cell array with a narrowed memory cell region. SOLUTION: Each memory cell includes a storage capacitor 3, an access transistor 16, a plurality of bit lines 2 oriented in a first direction, a plurality of word lines 8 oriented in a second direction, the second direction being perpendicular to the first direction, a semiconductor substrate 1 with a surface, and a plurality of active areas being formed in the semiconductor substrate, each active area extending in the second direction. Each of the access transistors is partially formed in the active areas and electrically couples corresponding ones of the storage capacitors to corresponding bit lines, wherein a gate electrode 19 of each of the access transistors is connected with a corresponding word line 8, a capacitor dielectric 38 of the storage capacitor has a relative dielectric constant of more than 8, and the word lines are disposed above the bit lines. COPYRIGHT: (C)2008,JPO&INPIT
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