发明名称 ANALOG MEMORY
摘要 According to a preferred embodiment of the present invention, an analog memory includes a first to third memory blocks. Each of the first to third memory blocks includes a plurality of capacitive elements for storing electric charges corresponding to an input signal, an output line for transferring the electric charges, and a plurality of MOS transistors each for changing connection between the capacitive element and the output line. When a signal is outputted from the output line to a buffer circuit by sequentially connecting the capacitive element to the output line in the first memory block, all connections between the capacitive elements and the output line are disconnected in the second and third memory blocks with the output line of the first memory block and the output line of the second memory block connected.
申请公布号 US2008074912(A1) 申请公布日期 2008.03.27
申请号 US20070861437 申请日期 2007.09.26
申请人 SANYO ELECTRIC CO., LTD.;SANYO SEMICONDUCTOR, CO., LTD. 发明人 ONAYA MASATO;SERIZAWA SHUNSUKE
分类号 G11C27/00 主分类号 G11C27/00
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