发明名称 Selecting circuit
摘要 A selecting circuit having minimal signal distortion caused by non-linearity of semiconductor switching elements includes a plurality of circuit groups each comprising an input terminal (INa); serially connected resistors (R 1 a, R 2 a) having a first end connected to the input terminal; a semiconductor switching element (SW 1 a) having a first end connected to a node between the resistors; and semiconductor switching elements (SW 2 a, SW 3 a) having first ends connected to a second end of the resistors (R 1 a, R 2 a). The circuit further includes an operational amplifier (OP) having an inverting input terminal to which second ends of semiconductor switching elements (SW 1 a, SW 1 b, . . . , SW 1 n) in respective ones of the circuit groups are connected in common, and an output terminal to which second ends of semiconductor switching elements (SW 2 a, Sb 2b, . . . , SW 2 n) in respective ones of the circuit groups are connected in common; and an output terminal (OUT) to which second ends of semiconductor switching elements (SW 3 a, SW 3 b, . . . , SW 3 n) in respective ones of the circuit groups are connected in common.
申请公布号 US2008074167(A1) 申请公布日期 2008.03.27
申请号 US20070902472 申请日期 2007.09.21
申请人 NEC ELECTRONICS CORPORATION 发明人 IRIGUCHI MASAO
分类号 H03K17/00 主分类号 H03K17/00
代理机构 代理人
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