发明名称 Placer with wires for RF and analog design
摘要 The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.
申请公布号 US2008077898(A1) 申请公布日期 2008.03.27
申请号 US20060528235 申请日期 2006.09.27
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 SUBASIC PERO;WANG XUEJIN;DENGI ENIS AYKUT;MOHAMMED IBRAZ H.
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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