| 摘要 |
PROBLEM TO BE SOLVED: To prevent hold errors during implementation of a scan test, wherein a scan chain is constructed of a plurality of flip-flops, in a semiconductor integrated circuit. SOLUTION: The substrate potential of a transistor in a portion, including one among a scan data input circuit part 601 inside a region 10 of a scan-type flip-flop circuit, a portion except a portion for performing high impedance control by a clock system signal inside a master part 604S or a slave part 605S, and a data output buffer part 606 is separated from a source potential of the transistor and a source potential and a substrate potential of a non-target transistor other than the transistor. At normal operation, the substrate potential of the target transistor is equalized to that of the non-target transistor for use, and at implementation of a scan test, the substrate potential of the target transistor is tested, by impressing a back bias to a side that is increasing in the threshold of the transistor. COPYRIGHT: (C)2008,JPO&INPIT
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