发明名称 FLOATING POINT ARITHMETIC DEVICE AND RADAR SIGNAL PROCESSOR USING THE SAME DEVICE
摘要 PROBLEM TO BE SOLVED: To shorten the processing time of a whole filter arithmetic operation even when it is necessary to convert the format of data to be processed from a fixed point format to a floating point format. SOLUTION: A filter arithmetic operation just after input is executed by a fixed point arithmetic operation, and the arithmetic result is converted to a floating point format. In a DSP handling with a floating point arithmetic operation, a calculation instruction, a memory access instruction and a floating point conversion instruction are optimally combined by considering that it is possible to simultaneously execute calculation and floating point conversion, and the floating point conversion processing which has been independently performed just after input in a conventional manner is simultaneously executed by the following filter arithmetic operation. Thus, it is possible to increase the efficiency of the floating point conversion processing, and to minimize the processing time. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008071170(A) 申请公布日期 2008.03.27
申请号 JP20060249817 申请日期 2006.09.14
申请人 TOSHIBA CORP 发明人 NAKADA AKIYOSHI
分类号 G06F7/57;G01S13/52 主分类号 G06F7/57
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