摘要 |
<p>An encryption processing device (100) includes an interrupt timing judging circuit (101). The interrupt timing judging circuit (101) has an interrupt timing judging register (101a), a transfer state reference unit (101b), and an interrupt timing judging unit (101c). The interrupt timing judging register (101a) stores a table (200) used by the interrupt timing judging unit (101c) for judging an interrupt of the transfer process of DMAC (102). The transfer state reference unit (101b) monitors how many bytes have been inputted to an encryption operation circuit (103) from the block which has been read from a memory (14) by the DMAC (102). An interrupt timing judging unit (101c) judges whether to switch the transfer object while the DMAC (102) is transferring image data according to the table (200) stored in the interrupt timing judging register (101a) and the monitor result (the number of transferred bytes) of the transfer state reference unit (101b).</p> |