Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics

摘要

A method of fabricating at least one damascene opening comprising the following steps. A structure (10) having at least one exposed conductive structure (12) is provided. A dielectric barrier layer (11) is formed over the structure and the at least one exposed conductive structure. A lower low-k dielectric layer (16) is formed over the dielectric barrier layer. An upper low-k dielectric layer (20) is formed over the lower low-k dielectric layer. An SRO etch stop layer (18) is formed between the lower low-k dielectric layer and the upper low-k dielectric layer and/or an SRO hard mask layer is formed over the upper low-k dielectric layer. At least the upper and lower low-k dielectric layers are patterned to form the at least one damascene opening exposing at least a portion of the at least one conductive structure, wherein the at least one SRO layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.