| 摘要 |
A multi port memory device is provided to tune internal bank command generation time easily by having equal internal command generation time of all banks, and to improve performance of tCK(clock time) of a DRAM(Dynamic Random Access Memory) core by decreasing variation of command signal generation time of each bank. According to a multi port memory device comprising a number of ports, a number of banks and a number of bank control parts, all bank control parts share all ports. A PLL(Phase Locked Loop) part generates a clocking signal. A serial part(605) is comprised in the bank control part, and receives parallel data applied from the ports in response to the clocking signal. A delay part is comprised in the bank control part, and delays the clocking signal. A command signal generation part(607) is comprised in the bank control part, and is synchronized with an output clock of the delay part, and generates a command signal by using an output signal of the serial part.
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