| 摘要 |
A video decoder is provided to improve data communication parallelism of an on-chip network structure, by forming the video decoder to have a mesh structure overall and a star-structure regionally. A video decoder comprises a plurality of switches(200-208) and a plurality of on-switch networks(301-303). The switches provide a parallel data transmission channel between a predetermined master module side and another master module side, a parallel data transmission channel between the predetermined master module side and a predetermined slave module side, and a parallel data transmission channel between the predetermined slave module side and another slave module side. The on-chip networks provide a regional type parallel data transmission channel between predetermined slave module sides, and a parallel data transmission channel between a slave module side of a corresponding region and a switch side. The video decoder has a mesh structure, overall, by the switches overall and a star structure, regionally, by the on-chip networks. |
