| 摘要 |
A method for forming a metal line of a semiconductor device is provided to secure reliability and to enhance device characteristics by forming a metal pattern having a desired width and a desired area. An interlayer dielectric(22) is formed on a semiconductor substrate(20). A narrow damascene pattern is formed on a first region having a narrow metal line by etching the interlayer dielectric of a metal line region. A wide damascene pattern is formed on a second region having a wide metal line by etching the interlayer dielectric of the metal line region. A conductive layer(21) is formed on the entire structure to bury the damascene pattern. A polishing prevention layer(23) is formed on the conductive layer of the second region. A polishing process is performed to remove the conductive layer except for the conductive layer of the damascene pattern to maintain uniformly the thickness of the metal line of the first and second regions.
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