| 摘要 |
<p>A method for fabricating a flash memory device is provided to reduce interference capacitance by utilizing an IPD(Inter Poly Dielectric) layer as a dielectric. A substrate(30) having a floating gate(32) is provided. An IPD layer(33) is formed on the floating gate. A control gate(34) is formed on the IPD layer. The control gate, the IPD layer, and the floating gate are etched. A cleaning process is performed using sequentially BOE(Buffer Oxidation Etching) liquid and ozone liquid so as to remove polymers generated from the etching process. The BOE liquid is formed by mixing NH4F and HF based on a predetermined ratio. The ozone liquid is formed by diluting the ozone liquid into pure water.</p> |
