| 摘要 |
A multiplexer cell ( 1 ) for converting an input signal (D<SUB>0</SUB>, D<SUB>1</SUB>) with a data input rate (f<SUB>D</SUB>) into an output signal (E) with a data output rate (f<SUB>E</SUB>), which in particular is twice the size of the data input rate, is proposed. For this purpose the multiplexer cell ( 1 ) according to the invention has a clock input connection ( 6 ) for supplying a clock signal (C<SUB>0</SUB>), the frequency of which is the same as the data input rate (f<SUB>D</SUB>), a first and a second data input connection ( 2, 4 ) for supplying a first or second input signal (D<SUB>0</SUB>, D<SUB>1</SUB>) at the data input rate (f<SUB>D</SUB>), a data output connection ( 6 ) for the output of the output signal (E) at the data output rate (f<SUB>E</SUB>), a first and a second master-slave register circuit ( 22, 24 ), the inputs of which are connected to the first or second data input connection ( 2, 4 ) and the clock inputs of which are connected to the clock input connection ( 6 ), for the flank controlled output of the first or second input signal (D<SUB>0</SUB>, D<SUB>1</SUB>), a delay circuit ( 18 ) the input of which is connected to the output of the second master-slave register circuit ( 24 ) and the clock input of which is connected to the clock input connection ( 6 ), for the delayed output of the second input signal (D<SUB>1</SUB>), wherein the delay is half a clock period of the clock signal (C<SUB>0</SUB>) and an XOR gate circuit ( 20 ), the first input of which is connected to the output of the first master-slave register circuit ( 22 ), the second input of which is connected to the output of the delay circuit ( 18 ) and the output of which is connected to the data output connection ( 8 ).
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