发明名称 Output buffer circuit
摘要 Disclosed is an output buffer including a first output buffer for data for receiving a data signal and outputting an output signal from an output terminal, a second output buffer with an output end thereof connected to the output terminal, and a selection circuit. The selection circuit receives a control signal indicating whether de-emphasis enabled or de-emphasis is disabled and performs switching control so that when the control signal indicates that the de-emphasis is disabled, the second output buffer is deactivated, when the control signal indicates that the de-emphasis is enabled, emphasis data obtained on delaying the data signal through a delay circuit is supplied to an input end of the second output buffer, thereby causing the second output buffer to operate as a de-emphasis buffer, and when a test control signal is of a value indicating an amplitude margin test, the data signal is selected to be supplied to the input end of the second output buffer.
申请公布号 US7348794(B2) 申请公布日期 2008.03.25
申请号 US20060500333 申请日期 2006.08.08
申请人 NEC ELECTRONICS CORPORATION 发明人 TANAKA MAKOTO
分类号 H03K17/16;H03K19/003 主分类号 H03K17/16
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