发明名称 Frequency/phase locked loop clock synthesizer using an all digital frequency detector and an analog phase detector
摘要 A frequency synthesizer, for integration in a low voltage digital CMOS process, controls a VCO using a dual loop structure including an analog loop and a digital loop. The digital loop includes an all digital frequency detector, which controls a center frequency of the VCO. The analog loop includes an analog phase detector and charge pump, which add phase coherence to the frequency controlled loop. The analog loop reduces the noise of the digital logic and VCO, and the digital control provides frequency holdover and very low bandwidth. The bandwidth of the digital loop is made smaller than the bandwidth of analog loop, and is preferably 200 times smaller. This parametric difference allows two separate control inputs to the VCO, one from the analog loop and one from the digital loop, with both inputs functioning relatively independently of each other.
申请公布号 US7349514(B2) 申请公布日期 2008.03.25
申请号 US20040796331 申请日期 2004.03.08
申请人 SEIKO EPSON CORPORATION 发明人 MELTZER DAVID;BLUM GREGORY
分类号 H03D3/24;H03L7/187;H03D13/00;H03L7/087;H03L7/113 主分类号 H03D3/24
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