| 摘要 |
A memory device comprising a DQS preamble test mode circuit is provided to enable rapid revision by controlling DQS preamble timing with test mode. A clock pulse input part(310) inputs a clock pulse. A first delay control part controls delay of the clock pulse. A DQS pre-output part(330) outputs a DQS pre-signal as much as the period where the output of the delay control part is overlapped with a preamble control signal. The clock pulse input part inputs a clock pulse corresponding to a falling edge if CAS latency includes decimal point, and inputs a clock pulse corresponding to a rising edge if the CAS latency does not includes decimal point.
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