| 摘要 |
An error correction circuit for use with an analog-to-digital converter (ADC) comprising a first switch and a second switch and correction capacitor arranged in parallel and coupled to the first switch. The second switch is also coupled to ground and the correction capacitor is also coupled to a reference voltage wherein the first switch is arranged to be active during a hold mode of the ADC and the second switch is arranged to be active during a sample phase of the ADC. ® KIPO & WIPO 2008
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