发明名称 METHOD FOR CALCULATING SOFT ERROR RATE, PROGRAM, DESIGN METHOD AND DESIGN APPARATUS OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a method for easily estimating a soft error rate (SER) of an SRAM or a memory circuit element in a product design stage. <P>SOLUTION: In the method for calculating the soft error rate, using a measurement result which measures a relation between an area of an information memory node diffusion layer of a memory circuit or an information holding circuit composed of a MISFET and a soft error rate (SER) with a plurality of information memory node voltages Vn as a parameter (S1), a first formula which shows the dependence of an information memory node area of an SER at the same information memory node voltage Vn is led (S2). Next, substituting the relation of the dependence of the information memory node voltage of the SER in the same information memory node area Sc for the first formula from the measurement result, a second formula is led (S3). Then, substituting an information memory node area and an information memory node voltage of a desired memory circuit or an information holding circuit for the second formula, the SER can be calculated (S4). <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008066598(A) 申请公布日期 2008.03.21
申请号 JP20060244699 申请日期 2006.09.08
申请人 NEC ELECTRONICS CORP 发明人 FURUTA HIROSHI;KADOTA JUNJI;MIZUGUCHI ICHIRO
分类号 H01L21/8244;H01L21/8242;H01L27/10;H01L27/108;H01L27/11;H01L29/00 主分类号 H01L21/8244
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