发明名称 CLOCK REGENERATING METHOD AND DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a clock regenerating device which regenerates a clock of stable frequency by suppressing jitters, the frequency converging in a short time even having a large deviation from a target frequency. <P>SOLUTION: The clock regenerating device includes: a means of calculating the difference between the amount of data stored in a buffer and a target value of the amount of data stored in the buffer, and controlling a frequency-variable oscillation means based upon the sum of a control integral value obtained by multiplying an integral value of the difference by an integral coefficient, a control differential value obtained by multiplying a differential value of the difference by a differential coefficient, and a control proportional value obtained by multiplying the difference by a proportional coefficient; a means of determining whether the regenerated clock frequency has converged based upon a threshold; and a means of varying the proportional coefficient and differential coefficient to smaller values when it is determined that the regenerated clock frequency has converged. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2008066831(A) 申请公布日期 2008.03.21
申请号 JP20060240023 申请日期 2006.09.05
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SAITO KOICHI;FUKADA YOICHI;KUMOSAKI KIYOMI
分类号 H04L7/00;H04L13/08 主分类号 H04L7/00
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