发明名称 DELAY MEASURING CIRCUIT IN SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a delay measuring circuit capable of readily inspecting delay failures which has become more likely to occur, with the increase in speed and in microfabrication of semiconductor integrated circuit LSIs. SOLUTION: A scan circuit includes a delay line, provided with a delay element 24 and a delay-mode selector 25, and a mode during test is set to a delay measuring mode, by setting "1" to a delay-mode enable DE of the selector 25. The state of the delay line is acquired, by inputting data transition to the delay line and by capturing the value of the delay line into a register by a capture clock. A scan out terminal delay value is calculated by shifting this piece of data, and the delay in the operating frequency is measured. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008064717(A) 申请公布日期 2008.03.21
申请号 JP20060245721 申请日期 2006.09.11
申请人 SHARP CORP 发明人 SUZUKI HIROTO
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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