| 摘要 |
A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.
|
