Methods and apparatus for reducing duty cycle distortion in a multiple-stage inverter

摘要

An apparatus and method are disclosed which may include a multiple-stage inverter circuit, having at least first, second, and third stages, wherein a ratio (R_m-(m-1)) between a size of a given one of said stages "m" to a size of a stage "m-1" immediately preceding stage m is less than N^(1/L-1), where "L" equals the number of stages in said inverter circuit and "N" equals the size ratio between the last and first stages of the inverter circuit.