发明名称 PHASE CHANGE MEMORY ERASABLE AND PROGRAMMABLE BY A ROW DECODER
摘要 An integrated circuit includes a non-volatile memory having memory cells each having a memory point and a selection transistor having a control terminal connected to a word line, a row decoder for supplying word line selection signals, and at least one generator for supplying memory cells with an erase or programming voltage or current. Word line drivers are interposed between the row decoder and the word lines, and are arranged for applying to a word line selected by the row decoder control pulses, the profile of which corresponds to a profile of an erase or programming voltage or current pulse. Application is for particularly but not exclusively to phase change memories.
申请公布号 US2008062752(A1) 申请公布日期 2008.03.13
申请号 US20070850507 申请日期 2007.09.05
申请人 STMICROELECTRONICS SA 发明人 GIOVINAZZI THIERRY;LA ROSA FRANCESCO
分类号 G11C8/00;G11C11/00 主分类号 G11C8/00
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