发明名称 Decoder circuit, driving circuit for display apparatus and display apparatus
摘要 A decoder circuit configured to output an analog voltage signal according to input digital data includes an operational amplifier, first selection circuit and compensation unit. The operational amplifier includes a plurality of input differential pairs and generates an output voltage by interpolating input voltages applied to the plurality of input differential pairs. The first selection circuit selects the input voltages applied to the plurality of input differential pairs from reference voltages according to the digital data. The compensation unit suppresses a fluctuation in a transient variation characteristic of the input voltages applied to the plurality of input differential pairs depending on a selection of the input voltages by the first selection circuit in case at least one voltage level among the reference voltages is changed.
申请公布号 US2008062021(A1) 申请公布日期 2008.03.13
申请号 US20070898017 申请日期 2007.09.07
申请人 SHIMATANI ATSUSHI 发明人 SHIMATANI ATSUSHI
分类号 H03M1/06 主分类号 H03M1/06
代理机构 代理人
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