发明名称 Phase-locked loop circuit
摘要 A phase-locked loop circuit includes a phase detector detecting a phase difference between a first clock and a second clock; a voltage controlled oscillator outputting the second clock based on an input voltage that fluctuates corresponding to the phase difference detected by the phase detector; and a selector selecting the first clock from a plurality of clocks based on a clock change signal that is transmitted to the selector while the input voltage is set substantially constant.
申请公布号 US2008063131(A1) 申请公布日期 2008.03.13
申请号 US20070892706 申请日期 2007.08.27
申请人 NEC ELECTRONICS CORPORATION 发明人 FURUTA MANABU
分类号 H03D3/24 主分类号 H03D3/24
代理机构 代理人
主权项
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