| 摘要 |
Semiconductor storage device of reduced layout area having memory cell rows accessed selectively. Memory cells, each including a programmable resistive element, are connected by a bit line to form a memory cell row. Selecting circuit for selecting a memory cell row includes a first NMOS transistor having first end connected to write amplifier, second end connected to the bit line, and a gate, and controlled such that, if the write amplifier outputs a voltage level on power-supply side after the block-select activating signal has been activated, a voltage of the same polarity as that of the power-supply voltage and exceeding the voltage level of the power supply is applied to the gate. A second NMOS transistor has first end to which the block-select activating signal is applied, a gate connected to the power supply, and second end connected to the gate of the first NMOS transistor.
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