发明名称 |
Fully salicided (FUSA) MOSFET structure |
摘要 |
A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.
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申请公布号 |
US2008064153(A1) |
申请公布日期 |
2008.03.13 |
申请号 |
US20070981496 |
申请日期 |
2007.10.30 |
申请人 |
AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH |
发明人 |
QIANG LO PATRICK G.;LOH WEI Y.;NAGARAJAN RANGANATHAN;BALASUBRAMANIAN NARAYANAN |
分类号 |
H01L21/336;H01L21/338 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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