发明名称 APPARATUS AND METHOD FOR CLOCK SYNCHRONOUS USE FOR DSRC SYSTEM
摘要 An apparatus and a method for synchronizing a clock in a DSRC(Dedicated Short Range Communication) system are provided to recognize a start point of a data frame by delaying and sampling a received signal for a predetermined time. An apparatus for synchronizing a clock in a DSRC system includes a signal delay unit(310), a noise removing unit(320), a frame detection unit(330), a phase fixing unit(340), a data extracting unit(350), and a synchronization detection unit(360). The signal delay unit delays a received signal for a predetermined time and performs a sampling of the delayed signal. The noise removing unit detects abnormal data of the sampled data and recovers the abnormal data to normal data. The frame detection unit detects a start point of the sampled signal and generates a reset signal. The phase fixing unit extracts a data clock signal in response to the reset signal, is synchronized with the clock signal of the sampled data and fixes the output signal. The data extracting unit buffers an output of the phase fixing unit sequentially and extracts data from the received signal. The synchronization detection unit detects a synchronization signal from an output of the data extracting unit.
申请公布号 KR100812692(B1) 申请公布日期 2008.03.13
申请号 KR20060136791 申请日期 2006.12.28
申请人 POSDATA CO., LTD. 发明人 BANG, JEONG HYUN;SHIN, HEE SUNG
分类号 H04L7/033;H04L7/02 主分类号 H04L7/033
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