发明名称 COMPUTER SYSTEM AND PROCESSOR CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To effectively execute prefetch according to the state of a cache line. SOLUTION: A processor 1 which reads a program including a prefetch command or a load command and data from a main memory 3 and executes them comprises an operation core which executes the program, a secondary cache 14 which stores the data on the main memory 3 every predetermined data storage unit, and a prefetch unit 13 which prefetches the data from the main memory 3 to the secondary cache 14 based on the request of prefetch from the operation core. The prefetch unit 13 has a secondary cache management table 131 comprising a region for maintaining storage state every position of the data storage unit of the secondary cache 14 and a region for reserving the request of prefetch, and a prefetch control part 132 which commands the reserved request of prefetch or the demand of prefetch from the operation core 10 to the secondary cache 14 based on the storage state of the table 131. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008059057(A) 申请公布日期 2008.03.13
申请号 JP20060232287 申请日期 2006.08.29
申请人 HITACHI LTD 发明人 TOMITA AKI;SUKEGAWA NAONOBU
分类号 G06F12/08 主分类号 G06F12/08
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