| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To avoid a decrease in a processing speed by satisfying setup time of a microprocessor even when a reading delay time from a memory increases because an operation clock frequency is comparatively at a low speed. <P>SOLUTION: When a gate element (9) is controlled by a control signal outputted from a general purpose port (Port), a signal state of a read signal terminal (/RD) of a memory (2A) is changed into an enable state and a disenable state in interlock with a signal state a read signal terminal (/RD) of the microprocessor (1). When a first operation mode is selected and the gate element (9) is controlled by the control signal outputted from the general purpose port (Port), a second operation mode is selected, wherein the signal state of the read signal terminal (/RD) of the memory (2A) is forcedly fixed to an enable state regardless of the signal state of the read signal terminal (/RD) of the microprocessor (1). <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
