发明名称 PHASE-LOCKED LOOP CIRCUIT AND SIGNAL GENERATOR UNIT
摘要 PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit and a signal generator unit having the above circuit, capable of promptly outputting a signal of desired frequency without greatly increasing the circuit scale. SOLUTION: A phase-locked loop circuit 1 includes a PLL 10 and a pretune signal generator 20 for generating a pretune signal S26 to bring the frequency of a signal S1 output from the PLL 10 into the frequency of signal S1 into the tuning frequency band of the PLL 10. The pretune signal generator 20 includes a counter 21 for counting the frequency of the signal S1 op from the PLL 10, an error decision section 23 for deciding whether or not an error value indicative of an error between the frequency of the signal S1 counted by the counter 21 and the pretune frequency is smaller than a predetermined threshold, and a memory 25 for storing the pretune signal S26 given to the PLL 10 when the error value becomes smaller than the predetermined threshold by the decision in the error decision section 23. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008060688(A) 申请公布日期 2008.03.13
申请号 JP20060232250 申请日期 2006.08.29
申请人 YOKOGAWA ELECTRIC CORP 发明人 TANAKA RYUTA
分类号 H03L7/10 主分类号 H03L7/10
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