| 摘要 |
A circuit for generating a constant voltage is provided to prevent an over current by automatically lowering an output voltage when the abnormality of the output voltage is generated. A clock generating stage(110) generates a comparison clock and a reference clock. A bias controlling stage(140), which is connected to the clock generating stage, supplies currents by outputting a bias source voltage through diodes connected to PNP and NPN transistors. A logic controlling stage(150), which is connected to the clock generating stage, converts into signals suitable for control input. A voltage converting stage(120), which is connected to the logic controlling stage, outputs a negative output voltage using switches and capacitors. An output buffer stage(130), which is connected to the voltage converting stage, removes noises through transistors and outputs a stable output constant voltage through PNP and NPN transistors.
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