| 摘要 |
<p>A semiconductor memory device and a manufacturing method thereof are provided to reduce resistance of a gate line by forming a drain gate line on an inactive region to have a line width wider than that of the drain gate line formed on an active region. A hard mask layer is etched by using a photoresist pattern to form a hard mask pattern(109). A metal gate layer(108), a conductive layer(107) for a control gate, a dielectric layer(106), a conductive layer(102), and a tunnel oxide layer(101) are sequentially etched to form a drain selection line gate(DSL Gate), plural word line gate patterns(Word Line), and a source selection line gate(SSL Gate). A line width of the drain selection line gate formed on an inactive region is larger than that of the drain selection line gate formed on an active region.</p> |
