| 摘要 |
A multilayer printed wiring board 110 includes a mounting portion 160 on which a semiconductor device is mounted; and a layered capacitor portion 140 which includes a first layered electrode 141, a second layered electrode 142, and a ceramic high-dielectric layer 143 provided therebetween, and in which the first layered electrode 141 is connected to a ground line of the semiconductor device and the second layered electrode 142 is connected to a power supply line of the semiconductor device. The ratio of the number of via holes 161a, each of which constitutes a part of a conducting path that electrically connects a ground pad 161 to the ground line of a wiring pattern and which passes through the second layered electrode 141 in a non-contact manner, to the number of ground pads 161 is in the range of 0.05 to 0.7. The ratio of the number of second rod-shaped conductors 162b, each of which constitutes a part of a conducting path that electrically connects a power supply pad 162 to the power supply line of the wiring pattern and which passes through the first layered electrode 141 in a non-contact manner, to the number of power supply pad 162 is in the range of 0.05 to 0.7. |
