| 摘要 |
<p>The circuit has reading and programming/erasing circuits (RCT, EPCT) including reading amplifiers (SAMPj, SAMPj`) and programming/erasing latches (PLTj, PLTj`) supplying respective reading and programming/erasing voltages (Vr, Vp) applicable to phase change memory cells (CELi, j, k, CELi, j`, k) of a non-volatile memory e.g. flash memory. A memory cell selecting blocks (SBjk, SBj`k) has selection sub-blocks (NSB, PSB) to connect the cells to the circuits, respectively, where the sub-blocks have respective conductivity type N and P-channel MOS selecting transistors (TN1, TN2, TP1, TP2). An independent claim is also included for a method of applying voltages to a memory cell by a memory cell selecting circuit.</p> |
