| 摘要 |
A method for designing a JPEG(Joint Photographic Experts Group)2000 encoder is provided to design and verify a system consistently by modeling an algorithm design according to a hardware structure and using the same test vector up to a design level to be composed. A JPEG2000 encoder is modeled in a UTF(Un-Timed Functional) level(S210), and a processing time of each module is compared(S220). A DWT(Discrete Wavelet Transform) module and a Tier-1 module are separated to implement the module having the longest processing time with hardware(S230). A control signal and a data signal are modeled by using a master/slave library of SystemC(S240). Time information is added by performing redesign in a BCA(Bus Cycle Accurate) level in which system operation is operated by synchronizing with a clock(S250). The design integrated with heterogeneous IP(Intellectual Protocol) is displayed by using the DWT module(S260). An MQ(Multi Quantizer) coder is generated in the Tier-1 module to raise relation between a software module and a hardware module(S270).
|
