| 摘要 |
A method and apparatus for dividing the frequency of an input clock signal by an odd integer is disclosed. The output of two asymmetrical clock dividers may be combined to produce a divided clock signal having a symmetrical waveform. Finite state machines may be used as asymmetrical clock dividers having desired duty cycles and relative turn-on and turn-off times to produce signals that combine to form a symmetrical divided clock signal. Alternatively, the output of an asymmetrical clock divider may be delayed by one input clock signal half-cycle and combined with the original asymmetrical signal to form a symmetrical divided clock signal.
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